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64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
INTRODUCTION
The S6B0107 (TQFP type: S6B2107) is an LCD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device provides 64 shift registers and 64 output drivers. It generates the timing signal to control the S6B0108 (64 channel segment driver - TQFP type: S6B2108). The S6B0107 is fabricated by low power CMOS high voltage process technology, and is composed of the liquid crystal display system in combination with the S6B0108 (64 channel segment driver).
FEATURES
* * * * * * * * Dot matrix LCD common driver with 64 channel output 64-bit shift register at internal LCD driver circuit Internal timing generator circuit for dynamic display Selection of master/slave mode Applicable LCD duty: 1/48, 1/64, 1/96, 1/128 Power supply voltage: + 5V 10% LCD driving voltage: 8V - 17V (VDD-VEE ) Interface Driver COMMON Other S6B0107 * * High voltage CMOS process 100QFP / 100TQFP or bare chip available SEGMENT S6B0108
Controller MPU
1
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
BLOCK DIAGRAM
V0L V1L V4L V5L
C62 C63 C64
C1 C2 C3
64 bit 4- Level Driver
V0R V1R V4R V5R
64 bit Bi-Directional Shift Register
DIO1 PCLK2 SHL
Data Shift Direction & Phase Selection Control Circuit
DIO2
M CL2
C R CR
OSC
Timing Generator Circuit
FRM CLK1 CLK2
V DD
V SS
V EE
DS1
DS2
MS
2
FS
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
PIN CONFIGURATION
100 QFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42
C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD DIO1 FS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 VEE V1R V4R V5R V0R NC CL2 NC
DS1 DS2 C NC R NC CR NC SHL V SS NC MS CLK2 CLK1 NC FRM M NC PCLK2 DIO2
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
S6B0107
3
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
PAD DIAGRAM (CHIP LAYOUT FOR THE 100QFP)
C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 V EE V1L V4L V5L V0L
1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 V EE V1R V4R V5R V0R
Y
(0, 0)
X
Chip size: 3450 x 4000 PAD size: 100 Unit : m
x 100
28 29 30 31 32 33 34 35 36
There is the mark S6B0107 on the center of the chip.
4
CR NC SHL V SS NC MS CLK2 CLK1 NC FRM M NC PCLK2 DIO2 NC CL2 NC
V DD DIO1 FS DS1 DS2 C NC R NC
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
PAD CENTER COORDINATES (100QFP)
Pad Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Pad Name C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD DI01 FS DS1 Coordinate X -1314.5 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1345.6 -1127.6 -977.6 -827.6 Y 1775.4 1630 1505 1380 1255 1130 1005 880 755 630 505 380 255 130 5 -120 -245 -370 -495 -620 -745 -870 -995 -1120 -1245 -1370 -1495 -1775 -1775 -1775 -1775 32 34 35 37 39 40 42 43 44 46 47 49 50 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 DS2 C R CR SHL VSS MS CLK2 CLK1 FRM M PCLK2 DI02 CL2 V0R V5R V4R V1R VEE C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 Pad Number Pad Name Coordinate X -677.6 -527.6 -377.6 -227.6 -77.6 113.8 308.7 458.7 608.7 758.7 908.7 1058.7 1208.7 1358.7 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 Y -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1495 -1370 -1245 -1120 -995 -870 -745 -620 -495 -370 -245 -120 5 130 255 380 505 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 Pad Number Pad Name Coordinate X 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1310.5 1185.5 1060.5 935.5 810.5 685.5 560.5 435.5 310.5 185.5 60.5 -64.5 -189.5 -314.5 -439.5 -564.5 -689.5 -814.5 -939.5 -1064.5 -1189.5 Y 630 755 880 1005 1130 1255 1380 1505 1630 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4
5
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
100 TQFP (S6B2107)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 V EE V1R V4R V5R V0R
C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
S6B2107
(100 TQFP)
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
NC CL2 NC DIO2 PCLK2 NC M FRM NC CLK1 CLK2 MS NC VSS SHL NC CR NC R NC C DS2 DS1 FS DIO1
6
C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 V EE V1L V4L V5L V0L V DD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
PAD DIAGRAM (CHIP LAYOUT FOR THE 100-TQFP)
C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44
Y
(0, 0)
X
Chip size: 3850 X 100 PAD size: 100 X 100 Unit : m
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 VEE V1R V4R V5R V0R
There is the mark S6B2107 on the center of the chip.
DIO1 FS DS1 DS2 C NC R NC CR NC SHL V SS NC MS CLK2 CLK1 NC FRM M NC PCLK2 DIO2 NC CL2 NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
PAD CENTER COORDINATES (100-TQFP)
Pad Number Pad Name Coordinate X Y Pad Number Pad Name Coordinate X Y Pad Number Pad Name Coordinate X Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD DIO1 FS DS1 DS2 C R CR
-1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1245 -1095 -945 -795 -645 NC -495 NC -345
1534 1409 1284 1159 1034 909 784 659 534 409 284 159 34 -91 -216 -341 -466 -591 -716 -841 -966 -1091 -1216 -1341 -1466 -1821 -1821 -1821 -1821 -1821 -1821 -1821
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
SHL VSS MS CLK2 CLK1 FRM M PCLK2 DIO2 CL2 V0R V5R V4R V1R VEE C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 C52
NC -195 0 NC 195 345 495 NC 645 795 NC 945 1095 NC 1245 NC 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697
-1821 -1821 -1821 -1821 -1821 -1821 -1821 -1821 -1821 -1821 -1466 -1341 -1216 -1091 -966 -841 -716 -591 466 -341 -216 -91 34 159 284 409 534 659
69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20
1697 1697 1697 1697 1697 1697 1697 1500 1375 1250 1125 1000 875 750 625 500 375 250 125 0 -125 -250 -375 -500 -625 -750 -875 -1000 -1125 -1250 -1375 -1500
784 909 1034 1159 1284 1409 1534 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822
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64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
PIN DESCRIPTION
Table 1. Pin Description Pin Number QFP (TQFP) 28(25) 40(37) 23(20), 58(55) 27(24), 54(51) 24(21), 57(54) 25(22), 56(53) 26(23), 55(52) Symbol VDD VSS VEE V0L, V1L, V4L, V5L, V0R V1R V4R V5R I/O Power Description For internal logic circuit (+5V 10%) GND ( = 0 V) For LCD driver circuit Bias supply voltage terminals to drive LCD.
Slelect Level V0L (R), V5L (R) Non-Select Level V1L (R), V4L (R)
Power
V0L and V0R (V1L & V1R, V4L & V4R, V5L & V5R) should be connected by the same voltage. 42(39) MS Input Selection of master/slave mode - Master mode (MS = 1) DIO1, DIO2, CL2 and M is output state. - Slave mode (MS = 0) SHL = 1 DIO1 is input state (DIO2 is output state) SHL = 0 DIO2 is input state (DIO1 is output state) CL2 and M are input state. 39(36) SHL Input Selection of data shift direction.
SHL H L DIO1 DIO2 Data Shift Direction
C1 ...... C64 DIO2 C64 ...... C1 DIO1
49(46)
PCLK2
Input
Selection of shift clock (CL2) phase.
PCLK2 H L Shift Clock (CL2) Phase Data shift at the rising edge of CL2 Data shift at the falling edge of CL2
30(27)
FS
Input
Selection of oscillation frequency. - Master mode When the frame frequency is 70 Hz, the oscillation frequency should be fosc = 430kHz at FS = 1(VDD) fosc = 215kHz at FS = 0(VSS) - Slave mode Connect to VDD.
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S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
Table 1. Pin Description (Continued) Pin Number QFP (TQFP) 31(28) 32(29) Symbol DS1 DS2 I/O Input Description Selection of display duty. - Master mode
DS1 L L H H DS2 L H L H Duty 1/48 1/64 1/96 1/128
- Slave mode Connect to VDD 33(30) 35(32) 37(34) C R CR RC Oscillator - Master mode: Use these terminals as shown below.
S6B0107 R Rf CR Cf Open External Open C R S6B0107 CR C
R
Slave mode: Stop the oscillator as shown below.
CR C
Open V DD
Open
44(41) 43(40)
CLK1 CLK2
Output
Operating clock output for the S6B0108 - Master mode: connection to CLK1 and CLK2 of the S6B0108 - Slave mode: open Synchronous frame signal. - Master mode: connection to FRM of the S6B0108 - Slave mode: open Alternating signal input for LCD driving. - Master mode: output state Connection to M of the S6B0108 - Slave mode: input state Connection to the controller Data shift clock - Master mode: output state Connection to CL of the S6B0108 - Slave mode: input state Connection to shift clock terminal of the controller.
46(43)
FRM
Output
47(44)
M
Input/ Output
52(49)
CL2
Input / Output
10
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
29(26) 50(47)
DIO1 DIO2
Input/ Output
Data input/output pin of internal shift register.
MS H DS2 H L H L L DIO1 Output Output Input Output DIO2 Output Output Output Input
11
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
Table 1. Pin Description (Continued) Pin Number QFP (TQFP) 22-1(19-1) 100-59(10056) Symbol C1-C64 I/O Output Description Common signal output for LCD driving.
Data L L H H M L H L H Out V1 V4 V5 V0
34(31), 36(33) 38(35), 41(38) 45(42), 48(45) 51(48), 53(50)
NC
No connection
MAXIMUM ABSOLUTE LIMIT Characteristic Operating voltage Supply voltage Driver supply voltage Symbol VDD VEE VB VLCD Operating temperature Storage temperature
NOTES: 1. Based on VSS = 0V 2. 3. 4. Applies to input terminals and I/O terminals at high impedance. (Except V0L(R), V1L(R), V4L(R) and V5L(R)) Applies to V0L(R), V1L(R), V4L(R) and V5L(R). Voltage level: VDD V0L = V0R V1L = V1R V4L = V4R V5L = V5R VEE .
Value -0.3 to +7.0 VDD-19.0 to VDD+0.3 -0.3 to VDD+0.3 VEE -0.3 to VDD+0.3 -30 to +85 -55 to +125
Unit V V V V C C
Note
(1) (4) (1), (2) (3), (4)
TOPR TSTG
-
12
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (VDD = +5V 10%, VSS = 0V, |VDD-VEE |=8 - 17V, TA = -30 - +85C) Characteristic Input Voltage Output voltage High Low High Low Symbol VIH VIL VOH VOL ILKG fOSC IOH = -0.4mA IOL = 0.4mA VIN = VDD-VSS Rf = 47k 2% Cf = 20pf 5% On resistance (VDIVCi) Operating current RON IDD1 IDD2 Supply current Operating Frequency IEE fop1 fop2 VDD-VEE = 17V Load current = 150A Master mode 1/128 Duty Slave mode 1/128 Duty Master mode 1/128 Duty Master mode External clock Slave mode 50 0.5 1.5 1.0 200 100 600 1500 kHz K mA A Condition Min 0.7VDD VSS VDD-0.4 -1.0 315 Typ 450 Max VDD 0.3VDD 0.4 1.0 585 A kHz
(1)
Unit V
Note
(1)
V
(2)
Input leakage current OSC frequency
(3) (4) (5)
NOTES: 1. Applies to input terminals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/O terminals DIO1, DIO2, M and CL2 in the input state. 2. Applies to output terminals CLK1, CLK2 and FRM and I/O terminals DIO1, DIO2, M and CL2 in the output state. 3. This value is specified at about the current flowing through VSS. Internal oscillation circuit: Rf = 47k, Cf = 20pF. Each terminal of DS1, DS2, FS, SHL and MS is connected to VDD and out is no load. 4. This value is specified at about the current flowing through VSS. Each terminal of DS1, DS2, FS, SHL, PCLK2 and CR is connected to VDD, and MS is connected to VSS. CL2, M, DIO1 is external clock. 5. This value is specified at about the current flowing through VEE . Don't connect to VLCD (V1-V5).
13
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
AC CHARACTERISTICS (VDD = 5V 10%, TA = -30C - +85C) Master Mode (MS = VDD, PCLK2 = VDD, Cf = 20pF, Rf = 47k )
CL2
0.7VDD 0.3VDD
tWLC
tsu
tWHC tDH
tsu
tWHC
DIO1 (SHL = V DD ) DIO2 (SHL = V SS ) DIO2 (SHL = V DD ) DIO1 (SHL = V SS ) tD
tD
tDF
FRM
tDM tDM 0.7VDD 0.3VDD tF tR tWH1
M
CLK1
tWL1
tD12
tD21
CLK2
tWH2 tF tR
14
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
Master Mode
Characteristic Data setup time Data hold time Data delay time FRM delay time M delay time CL2 low level width CL2 high level width CLK1 low level width CLK2 low level width CLK1 high level width CLK2 high level width CLK1-CLK2 phase difference CLK2-CLK1 phase difference CLK1, CLK2 rise/fall time Symbol tSU tDH tD tDF tDM tWLC tWHC tWL1 tWL2 tWH1 tWH2 tD12 tD21 tR/ tF Min 20 40 5 -2 -2 35 35 700 700 2100 2100 700 700 Typ Max 2 2 150 ns Unit s
15
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
Slave Mode (MS = VSS)
tF
tR
tWLC1 0.7V DD tWHC1 tSU tWHC2 tWLC 0.3V DD
CL2 (PLK2 = V SS )
CL2 (PLK2 = V DD )
tR tF tD 0.7V DD 0.3V DD tH 0.7V DD 0.3V DD tHCL
DIO1 (SHL = V DD ) DIO2 (SHL = V SS ) Input Data DIO1 (SHL = V DD ) DIO2 (SHL = V SS ) Onput Data
Characteristics CL2 low level width CL2 high level width CL2 low level width CL2 high level width Data setup time Data hold time Data delay time Output data hold time CL2 rise/fall time
NOTE: Connect load CL = 30pF
Output 30pF
Symbol tWLC1 tWHC1 tWLC2 tWHL tSU tDH tD tH tR/tF
Min 450 150 150 450 100 100 10 -
Typ -
Max 200 30
Unit ns ns ns ns ns ns ns ns ns
Note PCLK2 = VSS PCLK2 = VSS PCLK2 = VDD PCLK2 = VDD
(NOTE)
16
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
FUNCTIONAL DESCRIPTION RC Oscillator The RC Oscillator generates CL2, M, FRM of the S6B0107, and CLK1 and CLK2 of the S6B0108 by the oscillation resister R and capacitor C. When selecting the master/slave mode, the oscillation circuit is as following: Master Mode: In the master mode, use these terminals as shown below.
S6B0107 R Rf 47K CR Cf 20pF Open External Clock External Clock Open C R S6B0107 CR C
Internal Oscillation
Slave Mode: In the slave mode, stop the oscillator as shown below.
S6B0107 R CR C
Open
V DD
Open
Timing Generation Circuit It generates CL2, M, FRM, CLK1 and CLK2 by the frequency from the oscillation circuit. Selection of Master/Slave (M/S) Mode - When M/S is H, it generates CL2, M, FRM, CLK1 and CLK2 internally. - When M/S is "L", it operates by receiving M and CL2 from the master device. Frequency Selection (FS) To adjust FRM frequency by 70Hz, the oscillation frequency should be as follows: FS H L Oscillation Frequency fOSC = 430kHz fOSC = 215kHz
In the slave mode, it is connected to VDD.
17
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
Duty Selection (DS1, DS2) It provides various duty selections according to DS1 and DS2. DS1 L H DS2 L H L H Data Shift & Phase Select Control Phase Selection It is a circuit to shift data on synchronization or rising edge, or falling edge of the CL2 according to PCLK2. PCLK2 H L Phase Selection Data shift on rising edge of CL2 Data shift on falling edge of CL2 DUTY 1/48 1/64 1/96 1/128
Data Shift Direction Selection When M/S is connected to VDD, DIO1 and DIO2 terminal is only output. When M/S is connected to VSS, it depends on the SHL. MS H L SHL H L H L DIO1 Output Output Input Output DIO2 Output Output Output Input C1 C64 C64 C1 DIO1 C1 C64 DIO2 DIO2 C64 C1 DIO1 Direction of Data
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64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
TIMING DIAGRAM
1/48 DUTY TIMING (MASTER MODE) Condition: DS1 = L, DS2 = L, SHL = H(L), PCLK2 = H
C CLK1 CLK2
~ ~ ~ ~
1
2
3 ~ ~
63
64
1 CL2 FRM DIO1 ( DIO2 ) M V1 V1 V0
2
3 ~ ~ ~ ~ ~ ~ ~ ~
46
47
48
1
2
3 ~ ~ ~ ~ ~ ~ ~ ~
46
47
48
C1 ( C48 ) C2 ( C47 )
V4 V4
V1 V1
V0
~ ~
V5 V1 V5 V4 ~ ~
~ ~
V4
V0 ~ ~
V1 C47 ( C2 ) V4 V5 V4 V5 ~ ~ ~ ~
V0 V4
V1 ~ ~ V5 V1 ~ ~
V1 V4
C48 ( C1 ) DIO2 ( DIO1 )
V0
V1
V4 V5
~ ~ ~ ~
~ ~
Relation of CL2 & DIO1 ( DIO2 )
~ ~ CLK2
~ ~
CL2
~ ~ ~ ~ ~ ~
DIO1 ( DIO2 )
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S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
1/128 DUTY TIMING (MASTER MODE) Condition: DS1 = H, DS2 = H, SHL = H(L), PCLK2 = H
C CLK1 CLK2
1
2
3
23
24
1 CL2 FRM DIO1 ( DIO2 ) M V1 V1 V4 V0
2
3 ~ ~ ~ ~ ~ ~ ~ ~
126 127 128
1
2
3 ~ ~ ~ ~ ~ ~ ~ ~
126 127 128
C1 ( C128 ) C2 ( C127 )
V4 V5 V4 ~ ~ ~ ~
V1 ~ ~ V1 ~ ~ V1 V5
V0
V0
V4
V0 V1 C127 ( C2 ) V5 V4 ~ ~ V1 C128 ( C1 ) DIO2 ( DIO1 ) V4 V1 V5 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ V0 ~ ~ V4 V1 ~ ~ V5
V1 V4
V4 V5
Relation of CL2 & DIO1 ( DIO2 )
CLK2
~ ~
CL2
~ ~ ~ ~ ~ ~
DIO1 (DIO2)
20
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
1/48 DUTY TIMING (SLAVE MODE) Condition: PCLK2 = L, SHL = H(L)
1 CL2
2
46
47
48
1
2
46
47
48
~ ~ ~ ~
~ ~
M
~ ~
DIO1 ( DIO2 )
~ ~
~ ~
V1 C1 ( C48 )
V0
V1
V0
~ ~
V4
~ ~
V5
V1 C2 ( C47 ) V4
V0
V1
~ ~
V4
V1 V5
V4
~ ~
V0 V1 C47 ( C2 ) V4 V4 V1 V1
~ ~
V4 V5
~ ~
V0 V4 V1
~ ~
V4
~ ~
C48 ( C1 )
V5
V5
DIO2 ( DIO1 )
~ ~
~ ~
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S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
POWER DRIVER CIRCUIT
V DD
V0 V0L/R R1 V1 V1L/R R1 V2 R2 V3 R1 V4 R1 V5 VR V5L/R V4L/R To S6B0108
V DD
S6B0107
V EE
V EE
Relation of Duty & Bias Duty 1/48 1/64 1/96 1/128 Bias 1/8 1/9 1/11 1/12 RDIV R2 = 4R1 R2 = 5R1 R2 = 7R1 R2 = 8R1
When duty factor is 1/48, the value of R1 & R2 should satisfy. R1/(4R1 + R2) = 1/8 R1 + 3k, R2 = 12k
22
V DD 15 5 15
V DD FRM M CLK1 CLK2 CL V SS S1 - S
64 64
V DD V0R/L V2R/L V3R/L V5R/L V EE V SS S1 - S CL V EE CLK2 V5R/L CLK1 V3R/L M V2R/L FRM V0R/L
APPLICATION CIRCUIT
CS3 CS2B S6B0108 CS1B DB0 -DB7 RSTB E R/W RS
CS3 CS2B CS1B S6B0108 DB0 -DB7 RSTB E R/W RS
R1 R C
C1
V DD COM1
SHL
DS2
DS1
PCLK2
V SS V 0R/L C64 V 1R/L V 4R/L V 5R/L V EE
CLK1 DIO2 DIO1 CL2 M CLK2 FRM COM128
64CH COMMON DRIVER FOR DOT MATRIX LCD
C1
SEG1
SEG128
1/128 duty Segment driver (S6B0108) interface circuit
FS
CR
MS
LCD Panel
S6B0107 (master)
V DD
M CL2 DIO2
V 0R/L V 1R/L C64 PCLK2 FS DS1 KS2 SHL V DD CL CLK2 CLK1 M V 4R/L V 5R/L V EE V SS MS
CR R C CLK2 FRM
5
open open open open open
2
open open C1 FRM S 1 - S 64 V EE V0R/L V2R/L V3R/L V5R/L FRM M CLK1 CLK2 CL V DD S1 - S
64
V EE V0R/L V2R/L V3R/L V5R/L
CS3 CS2B CS1B DB0 -DB7 RSTB E R/W RS V SS
S6B0108
CS3 CS2B S6B0108 CS1B DB0 -DB7 RSTB E R/W RS V SS
S6B0107 CLK1 (slave)
5 15
15
V DD
V0
V1
V2
V3
V4
V5
MPU
V EE
RS R/W E RSTB DB0 - DB7 CS1B CS2B CS3
15
S6B0107
23

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